The present invention relates to a data processing system in which a program under execution may parallelly access operands in a plurality of spaces, and more particularly to a data processing system which stores in a hardware a portion of an origin addresses of a translation table used for a translation from a logical address to a real address so that a processing time to determine the base address based on the space address is shortened.
In a prior art data processing system which uses virtual addressing in the multiple virtual storage space, a range in which an instruction can designate a logical address by using a general purpose register is called a virtual address space, and one real address is imparted by the system from one virtual address space and a logical address. The process to determine the real address from the virtual address space and the logical address is called an address translation. The address translation is carried out for each virtual address space by using an address translation table (segment table and page table) defined by the system.
The address translation table is located on a main storage and an origin address (STO: segment table origin address) is given for each virtual address space. The address translation from the logical address to the real address is carried out by looking up the translation table by using the origin address STO.
Further, in order to determine one address space from the multiple virtual address space, a space address may be designated by a base space register which corresponds to a base register used in an operand logical address calculation of the instruction, and the space address may be determined by means such as look-up of the table provided by the system.
Such prior art technique for the data processing system is disclosed in U.S. Pat. No. 4,521,846.
The above prior art technique attains a relatively small scale multiple virtual storage space having up to eight virtual storage spaces which can be parallelly accessed by the program. The prior art system includes eight STO registers and the origin addresses in the STO registers can be correlated to space base registers which are paired with the general purpose registers. In the prior art system, an ordinary instruction uses the general purpose register in calculating the address and reads the STO correlated to the space base register from the STO register to realize the multiple space address. The prior art system requires a configuration which allows a maximum number of STO's permitted by the program in the architecture to be stored into the registers or memory.
In a more advanced prior art system, when the base space register is used for the memory access, a translation pair of the space address previously stored in hardware and the STO is used.
The prior art method is explained by using an L instruction as an example of a common memory access instruction. The L instruction has a format (called an RX format) shown by 13 in FIG. 1. The L instruction may also be executed in the first preferred embodiment of the invention illustrated in FIG. 1. One of 16 general purpose registers 11 is selected as an index register by four bits of the index register number field (X2), and one of the general purpose registers 11 is selected as a base register by four bits of the base register number field (B2).
The content of the selected index register, the content of the selected base register and the content of the displacement field are summed and the sum is used as the logical address of the L instruction to designate the address in the virtual space.
On the other hand, the base register number field (B2) of the L instruction selects one of 16 space registers which are paired with the 16 general purpose registers. One virtual space address is designated by the content of the selected space register.
In this manner, the virtual space address and the logical address designated by the fields X2, B2 and D2 of the L instruction are correlated to one area on the main storage by the system, and 32-bit data is written into one of the 16 general purpose registers designated by the four bits of the R1 field of the L instruction from the area on the main storage. Thus, the processing of the L instruction is completed.
A process to determine the real address on the main storage from the virtual space address and the logical address designated during the execution of the L instruction is now explained.
The space address is used to refer to the memory which stores therein the translation pairs of the space addresses and the STO's, read out the STO corresponding to the space address of the operand, translate the logical address of the operand to the real address based on the STO and access to the buffer storage and the main storage. If a desired pair of the space address and the STO is not stored in the translation pair memory of the space addresses and the STO's, the space address translation table on the main storage is accessed by the hardware to determine the STO. Thereafter, the buffer storage and the main storage are accessed.
In the prior art system described above, a process to determine the STO from the new space address (which is called a space address translation) is required during the process from the operand address calculation of the instruction to the operand data fetching. If an architecture permits the accessing by one or more programs to a number of virtual spaces, the STO registers or the STO translation pair memory must be large scale hardware, which leads to the increase of the overall hardware which performs the instruction operand address calculation to the operand data fetching (hereinafter referred to as an operand fetch unit). As a result, the performance of the data processing system is lowered.